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hiii
i have made ise project of 8& 16 up and down counter. i have made vhdl file of it and i am not getting how to create black box for reconfiguration.
please help
i have made up-down 16 bit counter in xilinx ise and now want to make reconfigurable partition and reconfigurable module in plan ahead . i have opened the project in plan ahead . then loaded netlist of 16 bit up down counter in . But this counter is become top module. and in plan ahead it...
hiii
i have made program of 16 bit up-down counter in xilinx ise and want to reconfigure with 8 bit up-down counter in a plan ahead . how to do recofiguration.
i am reading plan ahead tutotrial . i have created the project of 16bit up-down counter but i am getting how to create...
hiii
i have completed all the steps of synthesis in xilinx ise. translated and map process are updated . but when i run generate post map simulation model then waring is produce . warning is : NCD is not completely routed, some delays may be inaccurate.
please tell me how to solve this...
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