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Recent content by victor910

  1. V

    ISE xc2c64a, 2 output, phase.

    I will happy to look in the datasheet, please give me for example chip number.
  2. V

    ISE xc2c64a, 2 output, phase.

    it's not possible to replace your "??" 1. because for me need difference delay for every output. 2. it's not a range, it's must exactly amount.
  3. V

    ISE xc2c64a, 2 output, phase.

    no problem, clock in = 50000000Hz clock_out1 /2 = 25000000Hz, no delayed output clock_out2 /4 = 12500000Hz, must be delayed 7ns,compare to clock_out1 Clock_out3 /10 = 5000000Hz, must be delayed 19ns, compare to clock_out1 Clock_out4 /5 = 10000000Hz, must be delayed 4ns, compare to clock_out1 I...
  4. V

    ISE xc2c64a, 2 output, phase.

    ok, I understand need to be ordered Xilinx 7 series. I only found this one **broken link removed** , where to buying 7 series? found another one...
  5. V

    ISE xc2c64a, 2 output, phase.

    No, this does not work. I have the error when compiling: Line 33. Object clock_out of mode OUT can not be read. anyway, your proposal is only inverted signal probably. 20ns delay its only for example, but what we will do for delay 7 or 14ns? I will be very appreciated if you give precisely...
  6. V

    ISE xc2c64a, 2 output, phase.

    sorry, you must not understand what exactly need for me. clk = 45158400Hz, but this not important at all. my divider is working properly. a question in another, how to make one from clock_outS output later compare to another. I'm thinking before this simple task, and peoples with experience give...
  7. V

    ISE xc2c64a, 2 output, phase.

    First, big thanks to everyone for comments. Yes, it's XC2C64A chip. I wanna to put hear my full code project, but I had a warning from moderator how to put a code, he sends me a link with instruction but link do not open - - - Updated - - - this my full code: library IEEE; use...
  8. V

    ISE xc2c64a, 2 output, phase.

    I’m absolutely noob about this, please give me an example code.
  9. V

    ISE xc2c64a, 2 output, phase.

    First, thanks for this information. You are saving a lot time for me. Second, how to make little latency for second output in ”real life”.
  10. V

    ISE xc2c64a, 2 output, phase.

    I do not use the simulator. testing on the real device checked outputs with an oscilloscope. it's always different only 1ns. CLK = 45mhz outputs both 22.5Mhz the outputs are correct, but I wanna have one output more latest, for example, the latest 20ns compare to another output.
  11. V

    ISE xc2c64a, 2 output, phase.

    I have this code for a frequency divider ----------------------------- begin if (clk'event and clk='1') then count <=count+1; if (count = 0) then tmp <= NOT tmp; count <= 0; end if; tmp3 <= NOT tmp3 after 20 ns ; end if; clock_out <= tmp; clock_out3 <= tmp3; end process...
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