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thank you very much for replying.I am posting my code which I took from somewhere and modified it....
module add(
input wire signl, sign2,
input wire [3] expl, exp2,
input wire [7] fracl, frac2,
output reg sign_out ,
output reg [3] exp_out ,
output reg [8] frac_out
) ;
// signal declaration...
hello all,
I have two questions-
1.) I have written a behavioral code in verilog that uses some internal registers. During synthesis warning is generated that the signal is assigned but never used in the program so it will be trimmed during optimization part.Will it produce an...
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