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I simply meant that if I generate symbol for a verilog code for not gate, it works fine. But when I try the same for or gate, waveforms at output do not switch. The first and second waveform in image in question is input to verilog or and third waveform is output which clearly doesnt react to...
Hi. I have been trying to simulate verilog ams with components coded in verilog, veriloga and analog (pdk given mos).
I have done it and can see the wave forms but there is a problem, the or gate coded in verilog doesn't switch in output waveform window. rest all other gates are fine.
the...
Yeah. Actually, I was looking at various data sheets to find what value of Output and bypass capacitor and ESR to use for simulations. I didnt find anything very useful but got basic ideas how to go about the problem. Thankyou all :)
I have mentioned that the current is 100mA and the PMOS gate is driven by Opamp and source can be at 1.8 or higher. I don't see keeping PMOS in saturation a Problem with Vg>.8 V and VS=1.8V and Vd =1.5 V. Vth of low threshold voltage variant pMOS is around -400 mv.
I am aware of oscillations and that it is difficult but all I want to know is good output capacitance value to start with and I will use bypass capacitance. iI will also add additional zero to improve phase margin. I have access to cadence spectre and am doing this to learn some difficult...
Sorry, I actually meant I am using this .
I am using opamp and the inverting terminal is given 1.2V and opamp is driving PMOS whose source is at 1.8V. The output voltage required is 1.5V and is fed back to non inverting terminal of opamp. I hope you got this architecture. I want to know what...
I want to Design an LDO with voltage 1.5 V and load current of 100 mA. I am not able to decide
1. what value of output capacitance will be good and if I will need a bypass output capacitor.
I am using input of 1.2 V. If I use ceramic type capacitor,
2. what is the ESR value. Kindly help me...
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