Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi guys i'm new to this so bear with me.
I've been assigned to program a VHDL code for a 4bit down counter using half/full subtractors. I've got the sample testbench from my supervisor as shown below.
Counter testbench:
library ieee;
use ieee.std_logic_1164.all;
entity mycounter_testbench4...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.