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Recent content by vhdl4u

  1. V

    FPGA final year project for electronic engineering

    Yes, you can do.
  2. V

    FPGA based BPSK and DPCM

    Instead using Cordic generate sin wave with DDS. Then during input signal change change the phase of the sine wave by reading from different location. This works. I've done this. vhdl4u gmail com
  3. V

    FPGA final year project for electronic engineering

    Re: final year electronics project You can contact me at vhdl4u gmail.com
  4. V

    How to design a frequency divide by 3 signal generator

    Basically you neead to generate a counter where it count 0, 1 and 2. So, your 2-bit counter output is /3. Now, pl. note that that output will not have 50% duty cycle. If you need 50% duty cycle then you need more circuit.
  5. V

    Final year project idea in in electronics and communication field

    Re: final year project For that you can do FPGA based modulation scheme where input data is given to your system and output is either AM, FM or PM based on modulation selected.
  6. V

    FPGA final year project for electronic engineering

    You can do Viterbi Decoder, UART, AMFMPM etc.
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