Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The practical solution is to use the shift-reg as previously mentioned. I think this is the case for most fixed-length pattern detectors. But the goal of the school project is to learn a bit about FSM's, not to overcomplicate the problem to the point a FSM is the only solution.
I only get 13...
for me, marker-based code-folding is a requirement for a vhdl/verilog editor. I think this is just vim, emacs, and vscode (plugin) for the free editors. It sounds like notepad++ had this before 2010, but now it's only in languages like C# that have a #region feature.
verilog synthesis uses the sensitivity list and code to determine clock vs reset. This avoids the need for an "if rising_edge(clk) then" line.
so in this case, you have "posedge rst" which doesn't match the "if (!rst) begin".
idk, the last one is weird. it uses bitwise operations on 1b values. So an astute reader will question why a possibly multi-bit operator is being used. Did the writer think the operator was on multiple bits? why would the writer use a confusable operator?
a 1 bit message doesn't have a crc of 1 or 0 unless the polynomial is x^8 + 1.
in context, a serial version doesn't need to shift inputs 8 times before "interesting" things happen.
in more context, the crc is defined as message * x^crclen, (sometimes with a prefix before the message but that...
Let the polynomail be p = (x^8 + x^2 + x + 1). in terms of long division: rem(1/p) = 1. rem(x/p) = x, rem(x^2/p) = x^2 ... rem(x^7/p) = x^7.
rem(x^8/p) = x^2 + x + 1.
the first bit comes in, the value becomes 0x07 which would represent x^2 + x + 1. So that first input bit affected the state...
oh wait, this is double dabble. for some reason I thought those were else ifs. I'm dumb. it is intended to be unrolled this number of times. (although it can be serialized too). the amount of logic per iteration isn't terrible as everything is small sized. The resulting circuit is I think...
for this use-case, "double-dabble" is a better choice. but for a counting case you can optimize further. the trick there is to maintain the count in bcd on each cycle. the bcd to bcd+1 conversion is not as optimized as binary to binary+1, but the binary to bcd conversion scales worse.
@promach, are you familiar with lfsrs and forming the transition matrix to generate 2+ bits of output? This is an easier related problem. Or the general concept of how the connection polynomial works? This is a prerequisite to understand parallel CRC.
I've used non-power-of-two sizes in the past. not sure if I needed it for fifos specifically though. The goal is space savings when you know the max data size is a bit more than a power of two. this is more true if you know the max size is something like 33334 entries. suddenly the big fifo...
in polynomial long division, you want the highest power coef to become zero. if it is zero, this isn't hard to do.
For GF2 math, addition and subtraction are the same and both are xor.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
