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Recent content by verilogsh

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    I only have 61.44Mhz clock, how can I get 2Hz and 20Hz clock

    Re: I only have 61.44Mhz clock, how can I get 2Hz and 20Hz c The simplest way i see: 1) divide the system clock by 16 with ICS542 **broken link removed**. U will receive 3.84MHz clock. 2) Apply this signal as a system clock to some uC. For example MSP430F1101 ($1.2)...
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    Migration from Altera to Xilinx

    xilinx synthesis using a coregen design :idea: Another way to make a conversion has been found. :idea: Idea: I can generate ATOM netlist by Quartus (Altera). This netlist is a VerilogHDL module that contains configurations and interconnections of ALL LCELLs (logic cells) used in project...
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    Migration from Altera to Xilinx

    what is xilinx .bde file xfpgas Thank you for the explanation. I'll check Coregen, i think it will no problems with finding library equivalents. Thanks for help!
  4. V

    Migration from Altera to Xilinx

    ise device migration xfpgas Ok, lets say i already have my project as collection of Verilog modules that include LPMs. Then i run synplify in order to convert LPMs to Xilinx libraries. May you explane this point in detail? I mean, how to convert Altera libraries to Xilinx libraries using synplify?
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    Migration from Altera to Xilinx

    using xilinx netlist for altera maestor I have asked Xilinx, they advice to use AHDL2HDL utility, but it does not help me to convert whole project. :( r_e_m_y Yesterday evening i arrived at a conclusion that this is only way to make a migration. I think the scenario should be: - Load the...
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    Migration from Altera to Xilinx

    xilinx coregen modules altera The problem is that Altera project has block diagram (graphic) file as top hierarchy of the project. Other project files are connected to this top BDE file. These files are Verilog, or BDE (graphic) files that contain LPM's. The structure is very complex and...
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    Migration from Altera to Xilinx

    ahdl2hdl Hi! How to convert Altera project to Xilinx? Altera project has complex hierarchical structure made on Quartus for EP2A15 chip . The target Xilinx device is XC2V2000. What tools i need to do it? Thanks
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