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Recent content by verilog_always

  1. V

    Buffer Choice while doing clock tree Clock Tree Synthesis

    While using Small drive strengths - While optimizing tool may add more number of low drive strength cells in order to meet tran and other spec related . Large Drive strengths - Power consumption will more, as for I know.
  2. V

    when we use early and late derate

    Bze of On chip Variation factor , Derate values are applied both on Clock and Data paths.
  3. V

    Why do we need to run typical corner for signoff?

  4. V

    Encounter CTS-- CellHalo

    Thanks Owen li
  5. V

    Double height cells are used

    Why double height cells are used? How they are defined in LEF and what is its functionality.?
  6. V

    Encounter CTS-- CellHalo

    In Encounter CTS Spec file Came Across CellHalo for Clock Buffers? I need to know the use of it
  7. V

    effect of Clock Uncertainity

    Why the values for setup and Hold are different?
  8. V

    effect of Clock Uncertainity

    How different Values of Clock Uncertainity effects, in Placement stage? Do different values of Clock Uncertainity effect any Cts/Routing results?
  9. V

    Encounter CTS-- CellHalo

    Why CellHalo required between two clock buffers? Is there any purpose to use CellHalo for Clock Buffers?
  10. V

    doubt on CMOS Voltage

    Thank you for responding Now my doubt is On what factors thershod voltage depends? Another thing is Can't we decrease size dramatically of Transistor?
  11. V

    doubt on CMOS Voltage

    Hi Why can't we dramatically decrease the operating volatage of CMOS transistors( Means below 0.5v). What effects transistor if we decrease operating voltage suddenly? If any one as material please help.........
  12. V

    Combinational latch?????????

    What does combinational Latch mean???
  13. V

    Validation Vs Verification

    Verification is running ur design on Simulation tools and validation is running ur design in real time scenario eg on FPGA's
  14. V

    Help me write a Verilog code for 128 point data with 16 bit width

    Re: verilog code be clear on ur requirement
  15. V

    What does repeated START bit do in I2C protocol?

    Hi all, In this protocal if no ACk is sent Master can send STOP bit or Repeated START bit. What does repeated START bit do? Whether it Master has again Start from Scratch that is sending address of slave and so on?
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