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Recent content by venky442

  1. V

    Simple dspic programmer schematic

    dspic33 schematic Spanish: Hola Leonardo Por lo que yo se, para programar un dsPIC, necesitas que este alimentado por su propia fuente digamos 5 o 3 voltios, fijate en el datasheet del pic que quieres programar, ademas el VPP debe ser 12 a 13 voltios. Added after 30 minutes: Hi Leonardo...
  2. V

    In Circuit Debugger for Microchip

    **broken link removed** http://www.chez.com/silicium31/Electronique/PIC/FreeIcdEnglish.htm
  3. V

    Isolation - Digital or Optical?

    **broken link removed** The optical isolation is implemented between microcontroller and the serial port through which the micro communicates with a PC ..
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    [SOLVED] Project to replace CY7C64613 in the ICD2

    he functions of the CY could be determined by a combination of: -studying the CY firmware -studying the BL or dexxxxxx.hex files -studying the win driver -analyzing the USB traffic -LA on the ICD CPU interface
  5. V

    chopper stabilized opamp pss simulation problem

    the oscillator option is for real oscillator circuits which is not ur case, so u need to unselect it and put ur own clock generation model
  6. V

    Which tool can design broadband matching networks?

    Broadband matching If you need a broadband matching for LNA design, you can consider common-gate topology or shunt-feedback topology.
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    jobs in Antenna and RF System

    you can get these in VLSI and design (analog companies ) like amd, analog devices KPIT..
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    Materials about DLL programming

    Re: DLL programming does DLL mean that delay locked loop?
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    Why do we write Verilog test bench codes?

    Re: verilog test bench hi we need testbench for checking ouput with all possible inputs , but it canot be possible in xilinx at the same time. for very big complexity type of circuits ,test bench must be needed. so that for complicated project, testbench perform more coverage and flexible.
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    How to improve settling

    improve setting setting time(decreasing setting period) by maintaing the circuit in the critical rather than in either underdamping or overdamping. for that we need to insert resistance and capacitance compensatin with increasing Resistance value and decresing the capacitance so that we improve...
  11. V

    The impact of the shrinking process window and its effects on parametric yield.

    Re: layout design hi FRNDZ, as the device scalling is shrinked down,power consumtion will get increase due to leakage power dissipations,speed also increases as the device size(length decreases), electromigration propbems will take into effect,shortchannel effect(velocity saturation) effect...
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    Suggestions of DSP books with many examples

    spectral analysis of signals stoica u can get from here 1) Oppenheim "Digital Signal Processing" 2) P. Stoica, R. Moses "Spectral Analysis of signals", Upper Saddle River, New Jersey 07458 3) Prabhakar S. Naidu "Modern Spectrum Analysis of Time Series" CRC Press 4) N. Golyandina, V...
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    How BJT is formed in CMOS process??

    Parasitic BJTS can be formed in CMOS process whenever latch up occurs. Latch up mainly occurs only when N-well and P-substrate Impedances increase to very high. these can be avoided by using guaded ring structures and bury contacts..
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    How to increase CMRR of a telescopic opamp?

    Re: opamp CMRR can be increased by maintaining the higher differential gain than c ommon mode gain. for that mismatech between mosfets should be avoided
  15. V

    Documents on level-shift circuit design

    logic level shifter 24v Hi, do u want to design a level up or down shift circuits which can be useful in SOC applications with only sinlgle mail power supply. u can get these papers from IEEE with level shift circuits as the head line in the search box. these can reduces the no of...
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