Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by varunkant_2k

  1. V

    CMFB loop gain and phase margin

    Peak always shows the high energy level or in other words One or more poles are dominating the frequency response. Try to add any zero in the feed forward path by adding any buffer or by resistance in such a way it occures exactly at the dominant pole.

Part and Inventory Search

Back
Top