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i want to get the below two features,
1. after DC read a verilog design, can it write out the original verilog file?
2. after DC read a verilog design, if write GTECH verilog file, can it not change the wires name?
thanks very much!
fomality problem
hi,all guys,
i encounter problem with formality.
A is top module
B,C,D is sub module
when i run formality to only B module alone, B is set as top module,and no failing with result
but when i run formality to all module and A is set as top module,and have failing...
specify setup violation
hi,guys,
i encounter a problem with gate-level simulation, run in modelsim,it appear the following :
------------------------------------------------------------
r: ../../libs/modelsim_asic/fsc0g_d_sc.v(18445): $setup( negedge D &&& ~SEL:2841 ps, posedge CK:3 ns, 267...
Re: to power and area,which is the best for the LUT,PLA,ROM,
same as topic?
Added after 2 hours 1 minutes:
sorry, i must do it in ASIC?
have some peoples help me?thanks
hi, alls:
Now i am designning the vlc part of vc-1 standard for ASIC, but i doubt that there have so many talbe to look up, about one hundred pages table in vc-1 standard and only fourteen tables in mpeg2. so i have the following problem:
1, if i use combinatorial circuit with case or LUT...
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