Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vaisram

  1. V

    range of values for fixed point numbering

    Floating point numbers have a higher precision owing to the way they are represented. They have a sign bit, an 8 bit exponent and a 23 bit value. It is the exponent which gives the flexibility in floating point numbers. Have a look at IEEE 754 format for more details. In fixed point numbers...
  2. V

    help me out in fft design

    hi.. i have a model of fft generated from quartus.. its in vhdl.. i think u can use the IP from quartus..
  3. V

    equivalent of fork-join in vhdl

    is there any equivalent keywords in vhdl like the fork-join statement in verilog?
  4. V

    TCL tutorial or example to write testbench for VHDL code

    hi aiko89.. if you want to know how to write a testbench for any given code then check out WWW.TESTBENCH.IN website.. Here they talk about all verification concepts in detail and sample programs to help you out..
  5. V

    using linked list in vhdl

    i need a file write here because only after the entire write is complete by one module, the other module starts the read.. i tried a sample code for the linked list with the help you provided.. it worked fine :) .. thanks for your help .. now i shud expand on it..
  6. V

    using linked list in vhdl

    hi FvM.. im using VCS simulator and i think it does support VHPI interfaces.. but the requirements in the project are such that i need to do it only using vhdl and nothing else..
  7. V

    [SOLVED] Conversion of 8bit digit

    sry.. im not very conversant with matlab..
  8. V

    [SOLVED] Conversion of 8bit digit

    you will have to split hte data and then send... if data_16 is ur actual data to be transmitted, then send the LSB 8 bits of data_16 first, then take the MSB 8bits.. you can register the 16 bit data and then use the delayed version of it when ur sending the MSB 8 bits..
  9. V

    using linked list in vhdl

    i need the linked list because there are multiple files that i will be reading and each file size is huge.. once i have read a data, i want to free up the memory space by de-allocating the linked list.. in this way, my simulation will also be fast as i will be using hte system memory instead of...
  10. V

    using linked list in vhdl

    could you provide a few more details on this??? im groping in the dark.. the huge data is slowing down my vcs simulation..
  11. V

    using linked list in vhdl

    i need to read a file containing 3000000 (30 million) values and pass it to the DUT one at a time with a valid.. Is it possible to create linked lists in VHDL, read the file at zero time and load all the values into it? If the answer is yes, then how do i do it? Or is there any other method to...
  12. V

    [SOLVED] File read values exceed integer range in VHDL - How to handle?

    thanks for the idea.. :)
  13. V

    [SOLVED] File read values exceed integer range in VHDL - How to handle?

    I am developing a test benchf wher i need to read a set of values from a file and pass the values to the DUT. Now some of the values in the file exceed the integer range of (2^31) - 1 range (eg value 2382568613). How do i now read these values from the file?
  14. V

    24-bit width input data converted to 32-bit width data

    i guess you can append 0's to the MSB and then write to the SRAM. In this way ur original data would also remain the same.
  15. V

    Altera embedded multiplier performance

    you could also declare it as a multicycle path in the timing constraints.. that would solve the problem too..
See more

Part and Inventory Search

Back
Top