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i have selected the scan style as -clocked scan in DFT compiler, instead of mux based design
my flip-flop module is as below,
module FF(clk1,clk2,si,data,q)
wire clk;
clk=clk1|clk2;
always@(negedge clk)
begin
if(clk1)q=si;
if(clk2)q=data;
end
endmodule.
The above code fails in the compile -scan...
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