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Yes, the ports can be seen, but my issue is, their actual name is not getting displayed in the signal and debug window, instead, it is displayed as port0, port1 etc..
Please let me know if there is any solution for this?
Thanks,
Vaidhya.
Hi,
Is there any other way to view the SystemC module (SC_MODULE) ports and signals in Questasim other than using sc_trace?
I'm using the latest Questasim version. In its waveform debugger, I can view the module ports, but it is displayed as port0, port1 etc.. and not by their names. Please...
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