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Sequential cells should have an attribute " clocked_on : X " where X is the CLK, CP pin etc ..
Similarly clockgate ouput pins will have a specific attribute "clock_gate_output_pin " set to true to specifically identify them.
Let me know if this was what you were looking for
@huckle: I think you will need the .lib information for that . Once you have it there are many ways to find an answer to your problem.
I cant think of a way without it.
Okay, this is what is my own humble opinion.
The circuit captures the 0,1,3 bit of a 4 bit serial data stream.
Your max data delay (-> setup time ) should be less than the time from pos edge of first clock to the neg edge of second clock in the portion marked green with a circle.
Your min...
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