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Hello. In my top level entity i use package for create an array of std_logic_vector and this array is my output data type (output buses are this array). When i try to simulate it by using Modelsim i watch only input ports in "Wave" window (they have standart std_logic/std_logic_vector types) and...
Hello.
The code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
port
(
i_arst : in std_logic;
i_clk : in std_logic;
i_data : in std_logic_vector (3 downto 0);
o_data : out std_logic_vector (3 downto 0)
);
end entity;
architecture arch...
Hello everyone. I want to use some data from external file in my testbench.
Loading data from file:
------------------------------------------
--LOADING DATA FROM FILE-----------
------------------------------------------
type signal_storage is array (integer range <>)of std_logic_vector...
Hi everyone.
There are two questions about IFF Mk MA & Mk XII.
1) Open standart document has the definition:
Can someone tell how is codes created by using impulse from transponder's reply message?
2) In common case, we have a very large aircrafts on air and almost all of them has...
The first formula usually uses for random processes analysis. In this case operator E means average by realizations of random process.
The second formula usually uses for determinate signals analysis.
Write testbench and check it.
But:
1) Better use numeric_std library that std_logic_arith;
2) Usually when d = 0 q <= "11" and when d = 1 q <= "01", but it is not matter.
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