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It looks a lot to read, I will start to study it and then will come back to say whether that gives some improvement to my simulation or not, thanks!
No I am not using such filter, should I just put an ideal low pass filter at the output of my amplifier or is there any more proper way to do this?
So here I tried what you said, fs=8fin, fin=12.5MHz fs=100MHz, output sinusoid amplitude is (ideally should be) 400mV (800 mV pk to pk):
first noiseless trace
results that even without noise I have ENOB=8.3 while I would need 9
the noisy trace is:
SINAD decreases of 6dB thus looks like...
With spectrum I was not meaning the simulator (which is instead spectre) but the tool used to get DFT in ADEL (measurements menu> spectrum)
I am using the following version of cadence virtuoso:
(1) also or not? If not what is the differnce between (1) and (2)?
When using a DFT one has to...
Thanks a lot for your answers, I will try to be more clear regarding my questions
Why if fsampling is integer multiple of fin data won't represent the signal? Where can I read something about this? As far as I know from Nyquist-Shannon sampling theorem it is not excluded that sampling frequency...
Hi all,
I have some questions about ENOB measurement and improvement, I know it is a long post and many questions but I do not have an idea how to go on, I would be really grateful if someone could answer even to only a part of the questions.
I have to design a 9 bit accuracy amplifier with a...
Hi all,
As in the title I have two questions:
1)I have seen that when referring to some new technology of transistors it is said for example 28nm or some other length which as far as I have understood refers to gate length, is it correct?
If so why is that parameter taken into consideration...
Isn't it this the cadence virtuoso version?
I am using spectrum from measurements menu right now but I think there must be something wrong about how I set the DFT:
What I have is the following output (red waveform) from a switched capacitor amplifier for an ADC so at each period of the...
yes, sorry and thanks for replying, I am using cadence virtuoso version ICADV12.3-64b.500.21.
I have found the spectrum under measurements menu in ADEL and it calculates my parameters, only problem is that since my circuit is a switched capacitor amplifier, in the output spectrum I have a...
Hi all,
I am working with cad ADE_L and trying to calculate the ENOB for a switched capacitor amplifier and thus need its SNDR, so I have to find the RMS value of noise.
This is the way I would proceed, but not sure it is correct:
run transient noise simulation
calculate DFT of the output...
Do you mean that M4 should make a Vds of Q7/Q9? If it is not so how can I make sure to mirror the same current through Q8/Q10?
And if so how can I achieve that? I do not see how to relate Vds of Q7 and Q9 to Vds of M4
The point is that I do not think I can use wide swing current mirror you are showing because as you can see from the image I have attached, the Vgs of the bottom nmos should be provided by the common mode feedback circuit, so I cannot use the M1 and M2 transistors of your figure to get proper...
Thank you for your reply, unfortunately I am a beginner (student) and not sure what you meant, do you mean I should make as shown in figure, I added the red parts?
If so, the Vgs of the diode connected device would be different from the Vgs of the device I want to bias, because its source is...
Hi all,
I have been looking for a book or something that explained how to bias a fully differential folded cascode OTA since in all books I have found so far, the cascode transistors' gate voltage is always set as a not better defined Vbias without explanation about how it is generated, is there...
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