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Recent content by UsernameIsValid

  1. U

    Combining 2 digital signals?

    How do I combine 2 digital signals into one? Say I have signal with "pseudo-random" pulse and another signal with repeating pulse (like clock).. How do I combine those into one digital signal in verilog? Assuming they are both generated with the same clock (minimum pulse width is the same)...
  2. U

    Optical communication between two FPGA boards -- syncing clocks?

    I am working on something where I will have optical communication between two boards. One board will generate specific pulse, another will receive it. To simplify things, I will have same clock speed on both boards. However, how do I synchronize them to make the receiving FPGA pick up incoming...
  3. U

    How to sample a pulse or a clock into memory?

    Thank you. In my case its no. So I need to use asynchronous FIFO with 100-200MHz clock and something like 25MHz clock?
  4. U

    How to sample a pulse or a clock into memory?

    I am using Zynq development board, on which I am generating some kind of pulse inside PL. I want to sample this pulse/clock into RAM to be able to read it from software on the PS core (to get sort-of oscilloscope view). Since my pulse is currently being generated at about 100-200MHz, I guess I...

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