Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I have this vhdl code for creating ROM. How could be in verilog?
architecture a of test is
-- ROM declaration
type t_array is array (0 to 63) of std_logic_vector(4 downto 0);
constant ROM : t_array := ("10001","10010","10100", ...
Thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
