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Hello everyone;
I am designing a layout for a 6T-SRAM using Virtuoso Layout Editor based on TSMC 65nm PDK. I have drawn an isolated NP layer for each NMOS, but the layout area of SRAM is too large. Would it be possible to draw one large NP layer for all NMOS transistors?
Any help would be...
Hi
I need to design a voltage pulse generator to connect an nMOS gate terminal (65nm CMOS technology) by Spectre. Pulse amplitude is Vdd (1.2v), pulse width is 500ps (with acceptable tolerance), and both rise-time and fall-time are smaller than 100ps.
I would appreciate it if anyone could help me.
Dear researchers;
I started to carry out a monte-carlo simulation for an Operational Amplfier in TSMC 65nm technology with Cadence Virtuoso. In this way, I added relevant model libraries, so MC simulation proceeded successfully. However, I need to know process fluctuation parameters of CMOS and...
Hi all
I simulate one flip-flop via IC 6.17 with 1000 Monte-Carlo iterations in ADEXL. After finishing, I select all of 1000 output voltages plots to be shown in result browser. The next step is selecting all curves (traces) in result browser and exporting as csv file. Astonishingly, after...
Hi all
I am trying to run Cadence IC 6.16 through terminal (. .bashrc), but facing this error:
/bin/ksh: /lib/libm.so.6: version `GLIBC_2.23' not found (required by /bin/ksh)
And by typing ldd -v /bin/sh in terminal, I get this results:
linux-vdso.so.1 (0x00007ffd746c2000)
libc.so.6 =>...
Dear scholars
I am trying to find a cmos-bases cicruit to convert VDD voltage (1.2V) to 1.3V in 65nm CMOS technology. Is there any circuit such as level shifter to implement this idea?
Thanks,
Dear researchers and students;
I am trying to implement an SRAM in HSPICE by TSMC65nm technology. The restrictions on both width and length in this PDK are as follows:
Lmax= 2.401E-07
Lmin= 6.000E-08
Wmax= 6.010E-06
Wmin= 6.000E-07
In your opinions, is there any way to define a MOS...
Dear all researchers and students;
I am trying to simulate a simple memory circuit. But when I simulate the circuit in virtuoso ADE XL , I face this error:
{ (ADE-XL 1921): Failed to start new job after 3 attempts: Possible reasons could be:
1- The machine selected in the current job setup...
Thanks, dear Dominik.
According to your exhaustive explanation, by investigating gcc version and linked system library, I realized that the link between gcc in MMSIM directory and system library has been broken. After creating it, simulation can proceed very well. I really appreciate your...
Dear Dominik ;
Thanks for your answer.
According to your answer, I have realized that two versions of gcc is located at "/opt/cadence/INCISIVE152/tools.lnx86/systemc/gcc" (4.1 and 4.8). On the other hands, one version gcc (4.8) is found at this directory ...
Dear all researchers and students;
I am trying to simulate a circuit in which model of one of its elements is verilog-A code. But when I simulate the circuit in virtuoso -ADE (IC616 on Ubuntu 16.04-64bit), I come across these two errors:
ERROR (VACOMP-1008): Cannot compile ahdlcmi module...
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