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sir, i am using cadence encounter.
first i dealt with counter design. In that design,i used timing_report command and it worked. i had a constraints file too..
Now i deal with adder circuits,which are purely combinational...what should be the contents of the constraints file,since i donot have a...
can anyone tell me how to get the post layout delay of a combinational circuit like adder in cadence?
report_timing is not working and "NO contraints file found" is the message shown
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