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Most of the popular the front end tools having TCL shell in built , and they provide commands for performing various thing during a single run. More advanced users take that benefit and write TCL utilities inside the tool script to get job done. And for Perl I have seen , it is mostly used to...
Re: Formal Engine (PSL)
All the Formal assertion based verification tool supports now PSL and it seems to be popular among the designers. Formal methods not time consuming like simulators, often very very fast and give a Yes/No answer with resonable time.
Sometimes the problem with these types...
For transferring one bit signal ( which is typically control signal ) a standard synchronizer like
double flop synchronizer at the destination ( slow ) domain is enough. But as we are sending
data from "fast" to "slow" we need to care about the possibility of data loss too , which can
occurs...
Re: Timing analysis
STA tools validate the timing performance of a design by checking all possible paths for timing violations. It does the things in the same way that designer would does it manually, but with much greater speed and accuracy. For this STA tools splits the design down into a set...
Re: X propagation
If there are reachable X statement in your design , then these X's can be propagated. Hence in practice there should not be any reachable X assignment. This material maybe useful
https://www.arm.com/pdfs/Verilog_X_Bugs.pdf
verilog lint
In HAL custom rule can be coded. It provides standard VPI ( Verilog procedural interface ), VHPI ( VHDL procedural interface ) , CPI ( common front-end procedural interce) and HAL API , which is tool's own C programming application specific interface .
Re: Synthesis Pragmas
Pragmas or synthesis directives are specially formatted comments. Thye should not contain any extra characters other than what is necessary for the synthesis directive.
There are several types of pragmas supported by various RTL synthesis tool: Synthesis On and Off...
Transaction -based verification is a kind of verification which is done in higher abstraction level. Hence often it is done from system level prospective. Here concept of transaction plays the key role. Testbench often can be written in two layer. The top layer is used to model transactional...
Re: query in simulation
I think you can. Instead of directly writing test vectors inside verilog testbench , write them in .txt file. Then you can read those .txt files by verilog file I/O functions which becomes standard in verilog 2001. The C model should also read those .txt file by file...
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