Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ucassbo

  1. U

    Mentor Graphics ModelSim5.7d Fatal Error

    as far as the modeltech.exe file there are 2 of them in 4 different folders. they all have the same names but they differ in size. the first of them is 334KB and the other is 707KB. they play around in the following 4 folders: C:\...\...\Hds\bin C:\...\...\Modeltech\win32pe...
  2. U

    Mentor Graphics ModelSim5.7d Fatal Error

    and to the C:\Program Files\FPGAdvPersonal61\Hds\resources\downstream\modelsim still comes up with the same error. plus that modelsim comes up for a split second and disapears as sson as it reads the error.
  3. U

    Mentor Graphics ModelSim5.7d Fatal Error

    i don't have a printer installed, i have FIVE. i tryied moving the modetech.exe file from C:\Program Files\FPGAdvPersonal61\Exemplar\bin\win32 to C:\Program Files\FPGAdvPersonal61\Modeltech\win32pe but still it didn't work. I've read that other people had the 211 error as well but they...
  4. U

    Mentor Graphics ModelSim5.7d Fatal Error

    I get a # 0 0x0057ac02: '<unknown (@0x57ac02)> + 0xd2b52' # 1 0x0057adc2: '<unknown (@0x57adc2)> + 0xd2d12' # Corrupt Call Stack ** Fatal: (SIGSEGV) Bad pointer access. Closing vsim. ** Fatal: vsim is exiting with code 211. error when i'm invoking ModelSim from FPGA-Advantage. It...
  5. U

    How to take care of clock data recovery in a design?

    Re: clock data recovery....? use a data-strobe technique to recover the clock with an XOR gate. see DS-DE for more info.

Part and Inventory Search

Back
Top