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Recent content by tyagifaisal

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    [SOLVED] Verilog Synthesis using Synopsys Design Compiler

    Thank you. I stripped the top module off everything including the included modules, and started with one always block at a time. Took me a long time, but finally figured it out and pinpointed it to a few places, one at a time. Thanks for the idea of 'divide and conquer.' I am never going to...
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    [SOLVED] Verilog Synthesis using Synopsys Design Compiler

    Hi, I am trying to perform gate-level simulation of my circuit using Synopsys Design Compiler. My program runs during functional simulation and I get the right result as compared with my C code. I then used Synopsys and performed the Analyze -> Elaborate -> Compile Design steps and saved the...
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    Verilog Multiplier Module ... Inferred Memory Device as a Latch on Synthesis

    Thanks for the suggestions. I guess it is a horribly inefficient way of taking care of things in hardware. I do have some major reading to do before starting to tackle these problems by writing code!!!
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    Verilog Multiplier Module ... Inferred Memory Device as a Latch on Synthesis

    I guess I should have explained exactly what I wanted out of this design....I need 200+ of those multipliers and the sum of the 200+ outputs from the multiplier. mult_start sets off the trigger that the multiplier module should start. sig_start sets off the trigger that the sig module which...
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    Verilog Multiplier Module ... Inferred Memory Device as a Latch on Synthesis

    Do you mean something like: module mult(in1, in2, out, mult_start); input signed [16-1:0] in1, in2; input mult_start; output signed [32-1:0] out; reg signed [32-1:0] out_temp; assign out = out_temp; always @(in1 or in2 or mult_start) begin if (mult_start == 1'b1) begin...
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    Verilog Multiplier Module ... Inferred Memory Device as a Latch on Synthesis

    The above mult module is instantiated in a top module and I want the multiplication operation to take place only when mult_start has been triggered by the top module. That being said, I am assuming I do want the synthesis tool to infer it as a latch then and this is not unwanted synthesis...
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    Verilog Multiplier Module ... Inferred Memory Device as a Latch on Synthesis

    Hi, I have a Verilog multiplier module which is part of a big hierarchy. When I synthesize it, during the "Elaborate Design" phase (using Synopsys DCS), I get the message that the memory device has been inferred as a latch. I don't have any dangling if...else statement, and if the issue is with...
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