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I have a 1.25 kW LDMOS amplifier. It works fine at low powers of about 100 W. But beyond that I see an increase in the display on the power supply for the Gate to Source Voltage and Drain current increases too. The CRO also shows a fluctuating pulse. The output power on the power meter...
I have a power meter between the amplifier and the load. The output of the amplifier is connected to the first port of the power meter and the second port of the power meter is connected to the load.
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By 'they' do you mean the amplifier and the load?
Yes, they do have the...
I have an LDMOS amplifier. I am testing it using a power meter. When the second port of the power meter is connected to standard 50 ohm termination, everything goes well.
However when I connect it to my load which shows 50 ohm on VNA, the Gate to Source Voltage increases and there is an abrupt...
Hi
I had chosen Vgs as 2.47 volt to operate in Class AB mode.
However, when I did not get sufficient output power from the device, I started increasing the Vgs.
Yes, this is for MRI application.
How do I go about large signal matching?
Hi
I need to design a power amplifier at 64 MHz. The Freescale device (MRFE6VP61K25H) which I am using is capable of handling 1.25 kW of power.
I am attaching my design and results.
However, when I simulate in ADS for 1dB compression point, the maximum output power I get is 58 dBm.
I am unable...
Thanks!
I managed to fabricate the filter and get a good response at 64 MHz with 3.1 MHz bandwidth. I have attached the response obtained on VNA.
However, the insertion loss is still high.....around -10 dB.
Thanks for your input.
I will get low loss capacitors as G4BCH suggested and high Q...
Hi
I fabricated your design. I am getting a good S11 of around -16 dB but my insertion loss is too high (17 dB).
Can you suggest where am I going wrong?
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Hi
I fabricated your design. I am getting a good S11 of around -16 dB but my insertion loss is too high (17 dB).
I am...
Hi
I need to design a bandpass filter at 64 MHz with passband of 3 MHz and insertion loss of less than 0.5 dB.
I tried to design using lumped element LC topology. The simulation results are great but the very sensitive to value to the components.
Even a 0.1 nH of pF variation is causing the...
Thanks everyone!
So what I gather is that a Class AB amplifier designed using a single transistor can be used in applications where linearity is not a very important parameter.
Hi
I have a voltage generated at the output of my system and is acquired using cRIO a DAQ. The output is on an ethernet cable and is fed to a computer. I want to read this value in my MATLAB program and store it on a text file. I am new to this field and any help will be greatly appreciated. I...
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