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continuous time sigma delta adc
Active RC integrator has an amplifier in feedback loop and gives better linearity performance than a gm-C integrator. In a gm-C integrator, the transconductor is in open loop and hence you would expect lower linearity than an amplifier operating in a feedback...
Use the Net transport software. Use rtsp (real time streaming protocol).
When you save the link to a file instead of playing it in real player, it gives a link
to download as rtsp. Then input that link in the Net transport program.
Link for net transport software ...
Maybe this opamp architecture might help you meet the specs (this design simulated DC gain of 80 dB, GBW of 1.4 GHz and phase margin of 62 deg in TSMC 0.35 um CMOS technology) , though you may have have some difficulty with Vdd = 1.8 V :
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Send me...
The same effect is what user nandu has asked in the first message of the post and you are repeating it again. You are quoting a trivial first order effect that common mode noise should be cancelled if there is no mismatch and if Vin,diff = 0 (circuit is fully symmetric). If there is a slight...
Hi Nandu,
Your argument that the noise from the tail current source is common mode and hence should be rejected at the output is correct, but this rejection is based on the common mode rejection of the differentil pair, which I observe is bad because your tail current source output resistance...
The result may be large because at low frequencies - DC to 1 kHz, because you are mainly integrating flicker noise (for mos inversely propotional to area). Thermal noise contribution will be usually very small. So if you have small area devices, you flicker noise contribution will be large. The...
In analog artist window, after you run the noise simulation,
Select, Tools -> Calculator.
Select the node where you want the noise voltage as AC option in the calculator.
Then, there is an integral function called integ(). Give the initial and final value as 0 and 1 kHz respectively. (If you...
continuous delta sigma
Your question suggests that you don't understand the reason to go between continuous and discrete time model.
In a switched capacitor, every block works in the discrete time domain. The signal is sampled at the input of the SC filter, so in effect, the filter...
continuous delta sigma
This paper discusses how to model excess loop delay effects in continuous time sigma delta modulators.
Excess loop delay in continuous-time delta-sigma modulators
Cherry, J.A. Snelgrove, W.M.
Dept. of Electron., Carleton Univ., Ottawa, Ont. , Canada;
This paper...
Re: level shifters
The pole of the HPF depends on your application, ie, how low a frequency do you want to pass through and for most applications, the value of caps/resistors will not be huge as you describe them to be. Again, it is totally application dependent.
Using the Vgs of a diode...
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