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Recent content by TRUNGDPHAN

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    Anyone have wafer photos or link to get them?

    thanks for your links but I had done that, I can't get any pics without charge. Well, I have just seen more in Intel Corp. Thanks a lot.
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    Anyone have wafer photos or link to get them?

    Please help/give me wafer photos or link to get them! I have seen more in books but I can't find them out on internet. Thank you very much for your help.
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    Help: auto-scale current meter (from mA to 30A)

    Anyone know a design to measure the DC current from mAs to 20A? Thanks a lot!
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    XC3S200 capabilities...

    check this web: www.digilentinc.com
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    input 4 BCD numbers in kit spartan3 of Digilentinc. Help....

    I want to write code in order to input 4 BCD numbers using Kit Spartan 3 of Digilentinc. But my code has below errors: + some ports in disp_comp.vhd don't appear to assign pin. + some ports which I declared code for them (in display.vhd)is warned "UNUSED". Please help me correct these errors...
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    VHDL code for implementing NCO

    vhdl codes for nco I need a detail diagram of NCO architecture. Anyone got it? If yes, please share it for me? Thanks a lot.
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    Help about Software Defined Radio (SDR) using FPGA...

    Thank you for your document. Please help me to know step by step about the blocks in the document. Specially, the A/D block. Thanks
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    Ask about the timing in FPGA...

    Yes, that's all right. I said that one machine cycle is 1 microsecond if we use the 12 MHz crystal. if we use a different crystal, we should look up datasheet (normally, one instruction is calculated on oscillator period = 1/f). but in FPGA, we only have a delay time range from input to output...
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    Help about Software Defined Radio (SDR) using FPGA...

    That's a good document but figure of SDR system is not clear. Do you have any one else?
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    Ask about the timing in FPGA...

    Have you ever written code for the 8051 (or 89C51) microcontroller? in 8051, if you use Xtal 12MHz, one machine cycle is 1 microsecond. the instructions in the instruction set of the 8051 microcontroller are timing based on the machine cycle. So I use a loop (or timer ) to delay (base on the...
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    Help about Software Defined Radio (SDR) using FPGA...

    please help me to: + understand about SDR architecture. + point out an architecture which is using/is developing on the world. + applicate into an FPGA board (such as Sparktan 2E/3). + take an example code which is written for FPGAs (use Webpack software of Xilinx). Thanks a lot.
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    Ask about the timing in FPGA...

    Thank you for your answers. I use the XC2S200E Sparktan-2E chip of Xilinx. Clock signal is about 50MHz. I don't know how to relate the system clock signal with my clock signal which I use to write my program. Please show me to know clearly.
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    Where can I get old ICs for old boards ?

    Re: Help to get old IC... Thanks for your guides.
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    Ask about the timing in FPGA...

    Anyone has a source code which can delay 1 second using FPGA. Please give me a copy? Source code is written in MAX+PLUS II. Thanks a lot

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