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I am receiving this data on a parallel bus at the input of the FPGA (single ended). I am the receiver of this sync and data packets. The parallel bus is sent with a single ended clock (TTL levels). I need to decode the data packet and then send it to another module for decompression. Once I...
As both FvM and I mentioned, it's not clear what you're trying to do other than detecting a sync pattern. Then what? You have new data coming in every clock cycle, but you haven't said how many clock cycles of latency are allowed to do whatever it is that you're trying to do with the rest of...
I am adding more clarification...
The first pattern 0111111111111111111111111111111 [31..0] is like a sync pattern to start looking for a msg data packet right after. Again, the msg data package can start at any bit of the 32-bit bus input. So for example, as shown above, the start of the data...
I have a parallel bus of 32 bits changing value on every clock cycle @ 50 mhz
I need to detect pattern 0111111111111111111111111111111 [31..0] (bit 31 is a zero)
The pattern can start at any bit position of the parallel bus
This mean that I can get the 'zero bit" on i.e bit 19 of the...
"This means that there will be 32 equations in each branch of the code."
Ok ,it seems that there should be a crc_i (32) in each branch, correct?
However, somehow the cri_i(32) in a particular branch should only be affected by the numbers of bytes selected.
Can you give an example of this...
I think this was the same idea that I mentioned above about using byte enables ( I think) , however in your sample above. Does each of the "elsif" calculated a CRC value for that portion of the code? This also goes to my original question of how do you obtain the final CRC for the whole thing...
Yes , my example was for 16 in width just as an example. I guess when you say "complete logic for all sizes" it is not something this online tools will generate. This is the part that I am not sure how to implement. It seems that my previous idea of using "byte enables" and retaining the...
Again thank you . this is helping a lot!!
Assuming there are 8 bits left (data[7..0]) to clock in the equations below for the CRC generator
Do you mean that I need to implement in the CRC generator itself controls like byte enables that allow the last bits data[7..0] to be used for the...
Thank you for your quick response. I am very new to this so I have a lot of questions.
Are you saying that if there are 8 or 16 or 32 bits of data left to process in the data package, I should use the 8 ,16,32 CRC generator?
So if I calculate the CRC for the previous bytes with the 64 CRC...
hello:
ref : polynomial CRC32 for 802.3 (not pure Ethernet, but uses same polynomial )
Not very familiar with CRC but I have read a lot of information on the web.
I have seen places where you you can use online tools to generate VHDL code base on on particular polynomial and data width.
I...
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