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Recent content by tromeros

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    Problem in MMSIM 7.1 and ibm

    Hi everybody, I am doing some test design (an inverter) in order to get used to the IBM 90nm process cms9flp. I pass succesfully drc and lvs in assura and calibre and the assura qrc also ends succesfully. the problem arises when i run a DC simulation including the parasitics, using av_extracted...
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    Virtuoso hierarchical layout design

    Hi to all! I have the following problem. I made a layout component in Virtuoso that is simply a stack of metals with vias between them. When I use this component in my main layout design in order to connect two metals the connectivity checker shows that they are not connected. Is there...
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    Who use Cadence 610 ? ?

    ic61 The reason is that IC 6 uses openAccess and not CDBA as in the previous versions. So it will take some time to transfer the pdk's to the new environment. For practice cadence's gpdk is good.
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    Calibre is the industry standard as said before. If your process supports Calibre definitely go for it. For large and complicated circuits it is much faster. For smaller and simpler assura is also good.
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    question about transmission lines for a distributed VCO

    Hello everyone. I’m trying to design a cmos distributed differential VCO for a project, which means 2 parallel microstrip lines for the drain load and another 2 microstrip lines for the gate line. For the inverter i’m using the “delay variation by positive feedback” tuning technique, proposed...
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    LVS problem in nfets in ibm process

    Hello friends I continue this post since I haven’t yet managed to carry out a successful lvs using a single nfet (nfetx) in the ibm sige5am process. When I use pfetx I get a successful lvs check. I use a subc in the schematic and the layout. The difference in the netlist is that the nfet in...
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    LVS problem in nfets in ibm process

    Troy, if i use a substrate contact (subc component) I get the LVS error that in layout there is an additional component (subc) that does not exist in the schematic. So if you can give me more details that would be nice. Thanks a lot.
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    LVS problem in nfets in ibm process

    Hello, I am designing a LNA circuit using IBM 0.5um sige5am process. I am in the LVS process. I face the following problem. In my design I use both nmos kai pmos transistors. The pmos (pfetx in the process) has four terminals both in design and the layout and passes the LVS check without...
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    LVS problem about multifingered mos

    i tried the first option and it works! I am going to try the other options. So thanks for the help!
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    LVS problem about multifingered mos

    Hello I am designing a circuit in IBM 0.5 sige5am technology and I have the following problems when conducting diva lvs check. The design has a single mosfet. When the number of fingers of the mos is 1 then the lvs check gives netlist match. However when increasing the number of fingers, for...
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    Strobed noise analysis: noise skip count & number of poi

    Strobed noise analysis Hi to all, I want to specify the edge-to-edge jitter of a frequency divider. I have read the paper of Ken Kundert "Predicting the Phase noise and jitter of PLL - based synthesizers" (can be found at www.designers-guide.org ) which suggests the use of pnoise analysis in...
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    Chipset or a set of modules? Which to use?

    Hi to all, I want to design a communication system in order to get some measurements. I can either buy the required chips and connect them on a pcb or buy the items as modules and connect them via coaxial cable. Which solution do you think is better and why? Thanks in advqnce for your help.
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    Linux for IC 5.1.41 ?

    You can also use the CentOS distribution which is very similar to redhat, supports the newest hardware and can be found at www.centos.org. It works great with eda tools.
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    Phase Noise of A Closed Loop System (PLL)

    Hi to all, I would like to ask how to calculate the phase noise at the output of a closed loop system such as a PLL. I have seen the method described in https://www.designers-guide.org/ by Ken Kundert. He incorporates the jitter in the behavioural model of the subsystems of the PLL and...
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    Any issues of implementing TIA with 0.6um cmos proecess

    Have a look at this book. it is the book High Speed CMOS circuits for optical receivers

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