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Recent content by treehugger

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    Noise contribution in LNA?

    post lna contribution to system noise of course it is correct
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    how to match 2.7 mH+100ohm reactance to 8 ohms?

    0.5 ohms of resistance is included to model the wire resistance of the 7 windings.
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    how to match 2.7 mH+100ohm reactance to 8 ohms?

    yes there is! using the 2.7mH as an autotransformer in boosting fashion, and a 1.4nF capacitor. i asked this question to see if anybody is aware of this trick, and my head is still not very clear about this solution..: you are using the 7th winding as a tap and the rest 297 windings make it...
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    how to match 2.7 mH+100ohm reactance to 8 ohms?

    what is the wisest way of matching 2.7mH+100ohm reactance to 8ohms? at 80kHZ? thanks. Added after 9 minutes: ofcourse, without using inductors in the milli henries range.
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    Which one is more important? S11 or S22?

    depends on the stage of the system you are designing. I wouldnt care too much about s11 if that is my first stage amplifier. Added after 2 minutes: yeah but the first stages are better if they are also low noise and low noise is achievable only by good s11. so you see the comprimise. Added...
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    rectangular coil E field

    how would i calculate the E field induced in the plane parallel to the rectangular coil within which timevarying current flows? please help.
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    neuronal gating equation (multiplication) in spice?

    hi. i want to model the following equation in spice: dm/dt + (alfa(v)+beta(v))*m = alfa(v) where alfa and beta are dependent variables on 'v'. but evidently this requires multiplication. how am i supposed to handle the multiplication of two state variables in spice ? any suggestions?
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    design at high frequencies?

    at high frequencies TLs start to radiate. so, what design considerations should be applied at high frequencies?
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    Why do we use 6 transistors for storing 1 bit in SRAM?

    Re: sram design because sometimes speed matters. you need a relatively high capacitance at the end of the mos transistor to store the bit, and that slows down the read-write operation. ".. Ccell must be physically as small as possible to achive good density. However the bitline is contacted...
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    Implementing an 8-bit carry lookahead adder in cmosp18 technology

    Re: 8-bit adder among tree adders, kogge-stone is the fastest since it requires fewest number of series logic levels (4 levels for 16bit addition actually); however, that requires a good deal of hardware (in parallel) and dense wiring. brent-kung requires 7 series logic levels, hence it is...
  11. T

    why does a mos transistor saturate?

    hey, thank you for that!
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    why does a mos transistor saturate?

    what happens to Vp @ Vds>Vgs-Vt ?? doesnt Vp increase as we keep increasing Vds? if it does increase, how do you explain the constant current. if it does not incrase, why? thanks.
  13. T

    why does a mos transistor saturate?

    nice! however.. why the pinch off point has a constant voltage Vp?? What is Vp?
  14. T

    why does a mos transistor saturate?

    Ids remains (nearly) the same, even though the drain voltage is increasing with respect to source. Why? What is the underlying physics? thanks in advance Added after 18 minutes: i need a somewhat detailed explanation. an answer like "because the drain side is pinched-off" will not count...

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