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to the same ff, yes.. both setup and hold violations can occur because they are coming form different paths... (a slow path and a fast path).
setup and hold violations on the same path (exactly the same path)... i don't think there can be... i just don't see this happening.
hi pintuinvlsi,
the netlist that vlsitechnology is referring to is a gate level netlist (after synthesis)
not rtl netlist (behavior code). Agree, rtl netlist is most likely hierarchical, but for gate level netlist (after synthesis)... it can be either hierarchical netlist or flatten netlist...
Re: buffer cells vs delay cells in delay matching in placeme
picking delay cell or buffer cell, really depends on the amount of delay you are trying to insert and the space you have available.
in fast fast corner, 1 delay cell can equal 10 buffers.
so one is not better than the other...
hi,
flatten, is when the entire design is in 1 module (ie verilog, module, endmodule).
hierarchical is when you have more then 1 module for the entire design.
banckend tools are able to read in both flatten/hierarchical netlist.
hope this helps.
hi,
this is what i think i would see,
area, from 6 to 4, i am assuming placement area. any macros, that take up 5/6? if not, i don't see a problem here. routing, from 6 to 4, less rounting resources. may also cause timing issue due to detouring of nets. power mesh, only on 4? IR drop may...
hi,
i cannot go into detail, but in general, we can shield a net in between a pair of vdd net or vss nets because these are constant signals and will not introduce any crosstalk. picking vss or vdd to shield with really depends on how accessible vss/vdd is to that net. when shielding a net...
Re: MAGMA: Placement ISSUE
the easy way is to write a mtcl script for placement blockage that overlaps the mesh.
i am not sure if there is a simple command you can call, but i won't be surprise if there is.
good luck.
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