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Recent content by TON2

  1. T

    Large array in VHDL , too much resouces required any other options?

    Thanks for your replies, I am using Xilinx Vertex6 XC6VSX475T. So guess I have to study about using external RAM right? If any one have good references or manual please advise. Thanks again
  2. T

    Large array in VHDL , too much resouces required any other options?

    Large array in VHDL , too much resources required Hi, In 1 clock cycle, my design output output_real : out std_logic_VECTOR(15 downto 0); I have to run my design for 2048x64 clk and store all the 2048x64 output_real to be used later. Problem is I tried to store the whole output in a "Signal"...
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