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Recent content by tomsld

  1. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Thanks. I want to achieve max performance for each instantiated DSP. Now, for example, the 5th order lattice-ladder structure uses one DSP with 100% performance (320MHz after PAR) and latency of 20 clk for 16 mul, 5 sub and 10 sum operations (first C-AB, four times P-AB, five times C+AB, one AB...
  2. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Thanks a lot for criticism in my address :) 388MHz is achieved after PAR in ISE14.7. Basically i connect few BRAMs, DRAMs, SRLs with shared DSP. Xilinx claims that Fmax in range of 450-500MHz is possible for various filters. I have reached it only for single DSP macro. If i connect some other...
  3. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    There is some tricks in PlanAhead or I should manually edit design in FPGA editor after PAR? I use ISE only on this stage. And graph is drawn form synthesis report.
  4. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Now all is understandable. I pay the max speed price if variables are used. The graph is attached. If variables are used the DSP limit if reached with filter order M > 10 (because signals are 32b and each MUL utilizes 4 DSPs). If signals then two MUL operators in lattice part are shared over...
  5. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Hi again, I have chosen to work with ANN that have the filters on the inputs instead of weights. Filters are called latticearma (if Matlab) or lattice moving-average filter (in general). The Schur recursion is applied, therefore the k coefficients in the lattice part are replaced with...
  6. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Thank you. I will have it in mind.
  7. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Now I am more worried about the optimal final structure of the net. How can it be proved that the net described in VHDL level is optimal for selected FPGA chip. DSP load as Busy/Idle time? LUT/Slice? It would be perfect if it would be possible to describe a net in a lowest level as possible. I...
  8. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Thanks. I understood already. The MAC really not care about incoming data, we can write own processes to deal with any kind of neuron.
  9. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Boring papers :D :D :D for grant :D The precision is an another question. You mean that high level stuff only describes the design in some human understandable way. Then i have to code (ex. VHDL, manually) net or equations is such a way as higher level staff suggests? I still imagine that i can...
  10. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Thanks. My supervisor says, that it should be good and i could prove the efficient structure (resource utilization) of the net. But i think, that any matlab/C++/python code while is converted to hardware description level loses the optimality. So, from matlab level i can't to control and be sure...
  11. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Thanks. Unsupervised learning - maybe in the future. Let's say, than the weights are known. We gives the final equations for the algorithm and it tries to schedule the operations with max performance considering constrained resources. In the literature i found two types of ANN implementation...
  12. tomsld

    [SOLVED] Generation of desired size ANN for FPGA

    Hi, i'm first year PhD interesting in efficient implementation of ANN (espetially dynamic ANN) in FPGA. I need to clarify few issues and make sure about existing solutions to avoid double work not reinventing the wheel. After a survey i found many open and commertial tools for simulation and...
  13. tomsld

    Application of neural network on FPGA

    A simple proposal. Let him to sort apples and pears. Your net have two inputs. For example: first is a color, second is a roundness.
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