Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I work as a FPGA/LSI logic designer.
I am 43 years old now.
I am considering to change job now.
I have experienced logic verification using verilog,vhdl more than 10 years .
but,I have not had enough experience about logic designing.
Last month,I told circuit I designed is filled with bugs...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
