Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The following errors were found .. plz help me correct them
ERROR:Xst:1534 - Sequential logic for node <count1> appears to be controlled by multiple clocks.
ERROR:Xst:739 - Failed to synthesize logic for signal <count1>.
ERROR:Xst:1431 - Failed to synthesize unit <clk_gnrtr> .
The code is as...
HELP APPRECIATED >> THANK YOU IN ADV
Added after 1 hours 12 minutes:
An address latch enable signal control circuit for electronic memories, including: a circuit for sensing an external address latch enable signal; a switching circuit connected in output to the sensing circuit; an address...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
