Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by tmchen00

  1. T

    DC noconvergence in Hspice

    You can only set .ic for few critical nets, or it will occur some convergency problem at the middle of trancient simulation.
  2. T

    ADC reference voltage circuit

    I think you just need to fix the difference voltage of VREFP and VREFN. If both of them change when clock is switching(clock feedthrough), you don't need to take care of reference voltage recover time, right?
  3. T

    question about PLL divider value N > 2000

    Dear all, I need to use a PLL to generate a 25Mhz clock from reference clock 12KHz. But I have no idea if the feedback divider values N has any limit. Is the values (>2000) reasonable? Thanks. TM
  4. T

    Bandgap circuit and simulation.

    When use MOS device, be careful that W1/W2 is in inverse proportion to (Vgs-Vt)^2, not (Vgs)^2.
See more

Part and Inventory Search

Back
Top