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Recent content by titanic

  1. T

    Low latency integer divider..

    I meant shift and subtract divisions. It is the thing. I cannot use a library. I will do it all by myself...
  2. T

    Low latency integer divider..

    Hi, Im am trying to implement a binary divider with verilog . But conventional methods are too slow for me.. Does anybody know an algorithm eligible for low latency (2-3 clocks) binary diviision which can be pipelined.... thanx in advance
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    question about cadence virtuoso

    hi, I used to use mentor IC studio. I could define multi finger mos transistor with different widths, assign # of metal contacts customary and even orientation of the metal contacts. Now i use cadence virtuoso and i see very limited options on create instance mos.... which limits layout...
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    Nodeset for subcircuit

    It would be easy with hspice or spectre in text mode. But I could not figure out with analog environment and virtuoso ...
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    Nodeset for subcircuit

    Hi, For cadence analog design envirenment i built 32x32 memory array. I want to nodeset the sram latch. If i use simulation -> convergence aids -> nodeset , i am gonna have to nodeset every instance of the 6T memory cell. How can i nodeset subcircuit so that , every instance obeys that...
  6. T

    if - case optimization in verilog

    Hi, i am wondering which of the following verilog snippet is more efficient in terms of speed and area. --------CODE 1 reg [4:0] A if(A[4:0] = 5'b11111) jobs1 else if(A[3:0] = 4'b1111) jobs2 else if(A[2:0] = 3'b111) jobs3 else ifA[1:0] = 2'b11) jobs4 else if(A[0] = 1'b1)...
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    VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

    Re: VHDL netlist. Hi, thanx for the replies... I could fix it...
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    VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

    VHDL netlist. That line is the instantiation of the netlist... like Inst_0 : my_istance
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    VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

    Re: VHDL netlist. Iwill check it... ..There are no prior messages btw...
  10. T

    VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

    Re: VHDL netlist. Veriliog code itself has been tested and post simulation results have been passed. I added several blocks and it gives same message to all modules without exception.... Modules are connected through the amba AHB bus ...
  11. T

    VHDL netlist compilation error- @E: CD708 :xxx.vhd|Not a concurrent statement

    VHDL netlist. Hi, In libero, I wrote a verilog code and generated VHDL netlist of the code and connected VHDL netlist to another VHDL project. However, synplify gives the following error message after long compilation . @E: CD708 :"C:\AAAAA\XXXXX.vhd":82:22:82:35|Not a concurrent statement...
  12. T

    Migration to Linux Redhat Enterprise

    Hi, Our research group will change infrastructure in order to use Cadence and Synopsys tools with Linux Redhat Enterprise. We want to build a LAN for this. For such infrastructure what do we need beside the workstations. (License server or sth else). I need any suggestions (especially...
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