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Recent content by tisheebird

  1. T

    How to polarise the Deep N-Well (WB) or tap WB in the layout

    Hello I have done the layout but need to tap WB or polarise "DNW" so please anyone could tell me how we can do it.? I need to polarise it to VDD right..? Please guide me with the steps.
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    Behaviour of a designed circuirt

    I have designed a circuit and it gives me expected output. And when I plot s-plane plot with poles and zeros it looks like this: Position of poles: 1st pole: -5 MHz 2nd pole: -33 MHz Position of zeros: 1st zero: -33 MHz All the poles and zeros are only on the real axis (no imaginary term) on...
  3. T

    Stability of a designed system

    1st pole: -5 MHz 2nd pole: -33 MHz Zeros: 1st zero: -33 MHz... Do you think such a system is stable system..? Can we call it 1 pole system with the locations I have mentioned before.? I just know the location of the poles and zeros.. When I see the transient response, there is no ripple. But...
  4. T

    Stability of a designed system

    Thank you for your suggestions. Actually I would like to tell you the position of the zeros and poles: 1st pole- 5 MHz 2nd pole- 33 MHz 3rd pole - 550 MHz Zeros: 1st zero- 33 MHz 2nd zero- 550MHz. All the poles and zeros are on the real axis on LHP and not like in the above picture. I...
  5. T

    Stability of a designed system

    But in our basics we have studied that if a zero is exactly on top of a pole then the effect of that pole cancel's out..So which mean that pole as no influence right..? I don't have a transfer function. But when I see the s-plane plot in CAD tool, I have all poles and zeros in LHP and lie on...
  6. T

    Stability of a designed system

    I have designed a system which gives a nice response in the simulation. When I checked the poles and zeros plot, it has 1 dominant pole on the real axis and other poles (2nd and 3rd) are exactly with the zero on the real axis. So i have few doubts : 1. Can we call such system 1 pole system...
  7. T

    Design of a classical 1 stage op-amp

    yes you are right. thanks...also I would like to know if a system is a 1 pole system then do you need to check the relative stability or it is always stable.?
  8. T

    Design of a classical 1 stage op-amp

    Yes you are right. Here is my case. Please guide me what is the right way.. When I do DC simulation, the =+ve DC voltage is 1.62V and if my Vref is 1.62V then the amplifier is working. But if my Vref is suppose 1V then amplifier is not functional. So that means in the beginning, i have to set...
  9. T

    Design of a classical 1 stage op-amp

    Thank you. But when I give same inputs on both the inputs then I am have a nice AC plot and DC values. But the question is when I varry the input such as +ve input is 1.6V and -ve input is 1V then the DC points varry and transistors are not in saturation region. So am I doing it right by this.?
  10. T

    Design of a classical 1 stage op-amp

    Thanks a lot...But I have designed 1 stage op-amp. I am telling you the W/L of each transistor. Could you please check if the amplifier is performing okay. Actually in my whole system I have used this amplifier and the output of the system is coming good. But I really would like to know if the...
  11. T

    Design of a classical 1 stage op-amp

    Hello, I have designed a 1 stage op-amp with the bias current of 2uA. ICMR- is 0.7V and ICMR+ is 1.62V. I want to check the output impedance and gain of my op-amp. so could you please suggest what should be the input value so that i can see the output resistance and gain of the system...
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    How to remove DRC AAC.C.3 and AA.C..5 errors during the layout...

    I have Substrate and well ties...Still I require AA filling...I don't know how to proceed..?
  13. T

    How to remove DRC AAC.C.3 and AA.C..5 errors during the layout...

    How to add "dummy" transistors..?? I really don't understand.. my layout is compact now...
  14. T

    How to remove DRC AAC.C.3 and AA.C..5 errors during the layout...

    Sorry for the late reply.. AA.C.3 Sized AA density also inside NODUMMY region, should be min 0.20, for Window of 100*100 microns (AA.C.3) : Except where spacing is smaller than 8 Microns. AA.C.5 AA.C.3 Sized AA density also inside NODUMMY region, should be min 0.20, for Window of 100*100...

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