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Hi, Iam driving a N channel FET with a PWM gate drive. There are larger current spikes (upto 20 A) during turn on. Pls suggest methods to clamp this current spike. The switching frequency is 1.7 Khz. The peak drain to source current is 4 A. Iam using a STP60NF06L FET.
Thanks,
tilak777
Thanks Audioguru.
So is there always a trade off between the bandwidth and gain. So if we want a higher bandwidth then the closed loop gain will have to be less ??? what is the relation between bandwidth and stability (gain margin, phae margin) ???
Hi,
Iam new to SMPS design and Iam trying to understand the feedback loop compensation in flyback converters. I did go over a few materials but was still not able to understand the whole picture. Can anyone recommend some materials that will start with the basics ??
- tilak
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