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Recent content by Tieny

  1. T

    How to find the operating frequency for an ASIC?

    The frequency is depend on process, design margin ,.. If your FPGA board signoff @20Mhz , there are no reason you increase @30Mhz if you dont want to face with setup timing violation ,.. Tiep Ngo
  2. T

    DFT Visualizer Data View

    It means your FF.Q expected value 0 after unload (shift out the data to the scan chain) . I can explain more about it : Q 000 - 100 - 000 [shift in ] - [capture ] - [shift out] Tiep Ngo
  3. T

    Tool inserted DFT lockup latch is not transparent in functional mode (no test port)

    Hi , The lockup latch only active in scan shift path (FF1.Q -> LU.D -> FF2.SI ). So dont care about it on functional mode. Tiep Ngo
  4. T

    Running Deep Learning Based Plant Diseases Recognition

    Thanks, never try that but it's a good idea Tiep Ngo
  5. T

    Running Deep Learning Based Plant Diseases Recognition

    That's right, it just a dataset , you need a framework for Machine Learning like lite tensorflow on the Pi but the learning time will slowd due to CPU core and dont have GPU support. Tiep Ngo
  6. T

    Suggestions of RTOS for STM32F429

    I'm using OpenRTOS for my Discovery F4 kit . No issue till now. Tiep Ngo
  7. T

    DFT parallel pattern simulation mismatch analysis

    For parallel pattern simulation, the values are forced in SI pin of FF's by the simulator and shift 1 cycle in your load/unload procedure. What you should trace back is the clock , time it lanuch in the shift window and double check in your procedure Tiep Ngo
  8. T

    For DFT perspective ,what happens when there are no capture clock

    1. If your design is HATPG you can check OCC ( On-chip Clock Control ) for more info. DFT will create 1 scan_clock for this purpose. 2. If your design is not HATPG, it meant you have 3 clock domains , and all 3 of them will be scan_clock . For your statement " 1 clock will be active at capture"...
  9. T

    What is meant by Split CODEC IN DFT ?

    Can you point full statement in your document ? Tiep Ngo
  10. T

    LBIST low test coverage

    LBIST coverage is a tradeoff : if you want more cov , you need more logic --> more area, power, testtime ,... Tiep Ngo
  11. T

    MBIST DONE & GO failing conditions

    1. DONE signal : Test time not enough. GO bit will not compare. 2. GO/GO_ID signal :Should the failure on the controller / mem_inf. Tiep Ngo
  12. T

    [SOLVED] Post place & route netlist simulation is failing although STA is ok

    Some item you need to check : 1. Clock period ? Is it correct with your SDF . 2. Simulator option is correct with your SDF ? -mindelay with min conner and -maxdelay with max conner ? Using notiming check in your script ? 3. Your STA don't cover your pattern ? For example : this path is...
  13. T

    For DFT perspective ,what happens when there are no capture clock

    First , I will cause the error when you are doing insertion (C1 violation) and stop your flow ! Second , if your flop cannot capture clock , how can it operate in functional mode ?
  14. T

    Multiple scan clocks

    1. How to decide scan clock out of 4 clocks ? -> We also have OCC only choose 1 clock ( scan clock ) from the TOP level. 2. I have read somewhere that only one clock needs to be active , Why it is so ? -> You can check cross-clock domain ( which is unreal in most of functional function...
  15. T

    scan chain inside memory

    That's correct, in my experiment we also have ram sequential pattern to cover all logic from FLOP to D pin of memory.
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