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Recent content by tianxiaduzun

  1. T

    Does anybody here know how to use blind vias or buried via

    blind via in pcad Does anybody here know how to use blind vias or buried vias in PCAD(ACCEL) ? Thank you!
  2. T

    does anybody here has the 68hc16 complier from motrola?

    yes and thank you. Can you paste out?
  3. T

    Best way to learn VHDL

    learning with projec is the most efficient way
  4. T

    does anybody here has the 68hc16 complier from motrola?

    thank you
  5. T

    can I still find all the old posts before the changes?

    Hi, guys can I still find all the old posts before the changes?
  6. T

    xilinx timing constrain problem

    you should edit the constraint file, and include the constraint file when you synthesize it
  7. T

    Clock recovery problem with FSK demodulator

    try to ask some specialist in the field
  8. T

    Who can tell me what difference of them? (VHDL)

    I want to know too
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