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Re: Clock Gating
Clock gating saves power in both the clock tree buffers (which stop switching), and in the clock tree leaf cells (Flipflops).
Backend tools handle clock gating automatically during and after CTS (CTS being CG aware, and clock gating timing checks being applied after CTS), and...
If you sweep Vgs from 0.01V to 3.3V with a Vds set to 1.65V, then at some point the transistor will leave saturation. (e.g. Vgs > Vds + Vt) I assume in this case the gm values become questionable.
In normal design scenario's, does this pose a problem?
So do you reccomend sweeping the Vgs to a...
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