Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I've once seen an isolating protection stripped over a single 3.54mm pin header.
It is used to prevent connecting this pin and avoid making contact with other pins while connecting a logic analyzer on debug pins, for example.
The material reminds me of thermal shrink tubes, it is really...
thank you for the info.
I am using Vivado Simulator. Do you know how the simulator from Cadence is named, is it Allegro? I could only find their CAD tool. I need it for FPGA development btw.
hi,
my simulator does not support unconstrained record elements (VHDL-2008). I'm looking for another one. Any suggestions?
I know of some workarounds but I don't like them. Why is there no 2008 support in 2018? :thumbsdown:
thx
hello,
Cited from here:
https://www.edaboard.com/showthread.php?296002-trouble-with-edaboard-rss-feed-since-last-redesign-(-some-while-ago-). The problem has been solved.
however, it has not been solved for me:
for example, I get a FEED about "std logic conversion":
When I open it, it's...
I am subscribed to 4 forums:
PLD, SPLD, GAL, CPLD, FPGA Design
Microcontrollers
Embedded Linux and Real-Time Operating Systems (RTOS)
Digital communication
I did not unsubscribe from any threads (and am still not receiving any subscription mails).
@BradtheRad,
I am still unable to receive any email subscriptions from the forum activity. I am using a free email account from Google, which are very reliable. I also receive 'New Private Message' and 'Reply to thread' messages for threads I created.
I edited my profile settings and enabled...
Yes, this is the default behaviour of Vivado. I expected this been taken care of by the IP already, which it did as per multicycle.
The output clocks from the wizzard are beeing seen as synchronous by Vivado. This is not what I want them to be in this case.
Yes, this is what I want to do...
hello,
Vivado cannot close timing between two clocks, "vid_io_in_clk" and "vid_io_out_clk". Both IP cores have been configured for assynchronous buffering. I was expecting that the IP core are including constraints to declare the clocks between the data path as mutually exclusive (which is...
hello,
I subscribed to a few topics in this forum yet never received any email. I subscribed to the topics in forum tools, and am in fact subscribed to them. I set them to receive email notification. In my account settings I can also see that I am subscribed to it. My email is confirmed and...
To satisfying my curiosity, I was hoping for a somewhat generic example on how that affect design decisions, or the way I provide support to 3rd parties.
I received response from NXP:
[...] (for the product in question, ) market is no more here and there is no more support bandwidth allocated
I believe that means there is an EOL for the chip. Naturally to say they do not have any documentation for me.
Good news is, I received response from...
hello @KlausST,
Is this an option, for private use, non-commercial application? I did not try to contact the manufacturer for this. Signing an NDA would be no problem for me :)
hi,
I'd like to interface some Video output PHY's (HDMI, DP) with FPGA. I found some interesting boards, but they all have one common problem: NDA. For a hobby project, there's no way I'll get the needed documentation directly from the manufacturer.
I plan on relying on existing work...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
