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Dear engineer people
I 'd like to get your advice.
With Virsim, I wanted to simulate my gate-level netlist synthesized by DesignCompiler.
With the synthesized netlist and library file, I used virsim.
However, I couldn't simulate because the library file (~~~.lib) is Asic standard cell...
switch level simulation
I am looking for a gate-level simulation tool or switch-level simulation tool which supports Dynamic Timing analysis.(Not STA)
The tool can support that every input changes makes different delays.
I was wondering if I have well-defined UDP, VCS can support that?
or I am...
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