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Recent content by theHermes

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    assigning nets to shapes on different layers without vias in Allegro PCB editor 16.3

    @above, Ya true, it showed isolated shapes in my DRC report. I have now found a way to solve it by using vias. Thanks for the reply:-)
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    assigning nets to shapes on different layers without vias in Allegro PCB editor 16.3

    Hi, I am a newbie in PCB design and I am presently working on my first PCB design which is a capacitive sensor. I am drawing a 6 layered PCB and on the top layer I have all my components placed and routed completely. On the bottom routing layer, I need to make use of a net that I connected in...
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    Unable to understand notations used in deafult PCB footprints in OrCAD 16.3

    I am presently working on a PCB design for a sensor and I have just started learning Capture CIS and PCB Editor. I completed the schematic in OrCAD Capture and cleared all my DRC errors. I have also succeeded in creating a netlist and thereby exporting it to PCB editor. At this stage, I have a...
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    Capacitance calculation between long coplanar thin plates ??

    Hi. I am working on a project for the design of a capacitive sensor. In order to do that, I am required to compute capacitance using a simulation software like COMSOL. As I want to compare my simulation results with the theoretical results, I would like to know the formula to be used for the...
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    debugging errors in verilog testbench

    Can u help me debug errors in the fifo code? I am trying to find error but I have not suceeded in finding any. module newfifo(rst, clk, din, wr_in, //write_enable signal rd_in, // read_enable dout, //data_out...
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    errors in simulating the outuput of a synchronous fifo in verilog

    Hi, I have modified the code that I found on the net for my requirements.But, I realise that there are a few errors and I am unable to debug them.It would be great if you can help me with this. my code and testbench are as follows: module syncfifo( clk, rst, read_rq, write_rq...
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    modifying a 1 byte fifo output to 15 bytes in verilog ??

    Hi, I have designed a program for getting the output of a 8-bit fifo while taking the value fifo depth as 15 .Inorder to transmit my data, I need to wait for 15 bytes of information. Can u guide me as to how I should write a code for collecting 15 1 bytes of data till I get 15 bytes...
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    [SOLVED] need help in debugging the data_out output of synchronous fifo in verilog

    Hi I have written a code for synchronous fifo and added a testbench as well. I have obtained the results but I am not able to understand the data out signal. I am not able to understand the meaning of the dout waveform.Kindly help me. `timescale 10ns / 1ns module fifo2 (wr...
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    [SOLVED] help in correcting errors in fifo verilog code

    the code now has no errors. thanks a lot!!
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    [SOLVED] help in correcting errors in fifo verilog code

    HI, this is my code for synchronous fifo.I have tried to correct errors as much as possible but I have not suceeded. The error it says is illegal left hand assignment and shows many places.but I don`t know how to correct? Thanks for ur help. `timescale 1ns / 1ps module fifo2 (wr...
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    evaluation of erros in clock divider in verilog

    I need to design a clock divider as part of my verilog program for SPI but unfortunately I have a few errors and I am not able to correct the errors. the code is as follows: module clockdivider(mclk,rst,sclk); input mclk; input rst; output sclk; reg [7:0]divide; integer i; always@(negedge...
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    Verilog examples of how to implement a master/slave SPI

    hey, I cant see the code now. can someone help me by reposting the code if possible. thanks a lot!!
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    need help in designing a PCI express card in OrCAD

    Dear friends, I have been assigned a project wherein I need to design a PCIe to Peripheral controller in OrCAD.As further information,I have been given a block diagram of the PCIe and nothing more. Can someone tell me how to get a headstart to this problem? Do I have to use OrCAD capture for...
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