Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by The_Dutchman

  1. T

    Coaxial cable capacitance

    Thank you all for giving me a more clear sight on how this works as I was confused with the capacitance stated in the datasheet, now it is more clear to me. I also looked up some video's on youtube on this topic and basically I learned that you can drive a coax with whatever impedance you want...
  2. T

    Coaxial cable capacitance

    Hi Barry thanks for the reply. Yes I understand because of the voltage divider. But my concern is more the capacitance of the coaxial cable. At what speed will I be able to switch? Is this coaxial transmission line really 6.7nF of capacitance I need to consider, or don't I need to consider this...
  3. T

    Coaxial cable capacitance

    Dear All, I'm planning on using a transistor to drive a 75 Ohm coaxial line (RG6) with just a digital signal. From collector to VDD there will be a 75 Ohm resistor. The signal at the collector is than AC-coupled onto a RG6 coaxial cable. At the end of the long cable (100m, neglect the...
  4. T

    Input & output delay in mixed signal chip - RTL Signal Integrity

    Hi ~Sam, Thank you for your reply. On point 1 the input constraints, I'm not sure I understand how they are asynchronous. The inputs are 5 bits parallel. The modules I will be using are in the attachment (I will use the 7Gb/s generator module) so these generate this data on the rythm of the CLK...
  5. T

    Input & output delay in mixed signal chip - RTL Signal Integrity

    Hi everyone, I'm an analog designer performing my first mixed-signal chip now and I have some confusion about input and output delay constraints. Basically I have a 5-bit thermometer decoder now written in RTL which takes it's input data from the bondpads of the chip and the output of the...
  6. T

    Current Steering DAC output matching, what's the difference?

    Hello all, I was looking into current steering DAC's output matching, and I was a bit confused, why do they match like this?: And why not like this? For me it seems that impedance levels are the same? Transformer transforms 50 Ohm load to 50 Ohm on primary, 25 Ohm above center tap, 25 Ohm...
  7. T

    Virtuoso Custom Inductor Connectiviy Short Circuit

    Virtuoso Custom Inductor Connectivity Short Circuit Hello Everyone, I'm using a Virtuoso connectivity driven design flow. If I use inductors from the PDK, they appear as a symbol in my schematic with 3 terminals (+ - and bulk) and they also have the 3 corresponding pins when generated in the...
  8. T

    ADS Sparam mini-circuit balun 4-port but s3p?

    Re: ADS Sparam mini-circuits balun 4-port but s3p? Is it possible to elaborate on that? Maybe a reference or a paper so I can understand it? Any idea how can I get a wideband 12Ohm (balanced) to 50 Ohm (unbalanced) transformation?
  9. T

    ADS Sparam mini-circuit balun 4-port but s3p?

    Re: ADS Sparam mini-circuits balun 4-port but s3p? Thank you for your reply, however I don't want to use it this way. I would like to do a 50Ohm to 12.5Ohm conversion, so is it also possible to add a ground at the secondary and have the differential output on the primary?
  10. T

    ADS Sparam mini-circuit balun 4-port but s3p?

    ADS Sparam mini-circuits balun 4-port but s3p? Hello all, I'm used to working with ADS a little bit, but I can't seem to understand to simulate the TCM4-452X+ wideband balun from mini-circuits. I downloaded the s3p-file from over here: **broken link removed** Datasheet is here: **broken...
  11. T

    Wideband decoupling switching load (DC-GHz range)

    Hello all, For a wideband load I'm trying to design the power supply decoupling. The load pulls about 200mA DC current from my power supply with about 100mA of amplitude peak current at 3V supply. This peak current is at frequencies from about DC to 2GHz (multi-carrier signal) but for now I'm...
  12. T

    [SOLVED] Cadence simulation P1dB vs. frequency

    I managed to get it working using the hb simulation, and also using the pss simulation. Putting frf in the beat frequency was the right approach and put prf as sweep variable 1 and frf as sweep variable 2. However I think harmonic balance hb simulation is better because it generates multiple...
  13. T

    [SOLVED] Cadence simulation P1dB vs. frequency

    Hi all, For my design in Cadence I would like to simulate linearity over frequency. So far I had no succes. I'm using the ADEXL environment. I can successfully simulate the P1dB at a single frequency using a PSS analysis where I sweep my prf input power using a single input frequency & auto...
  14. T

    [SOLVED] Layout hierarchy PIN connectivity issue

    You have to make sure to put the extract connectivity level high enough (>0) so connectivity is extracted to the lower hierarchical levels. This can be found under Options-> Layout XL-> Connectivity tab -> Hierarchy Controls -> Extract connectivity to level (fill number of hierarchy to check)...
  15. T

    [SOLVED] Layout hierarchy PIN connectivity issue

    Hello all, I have a connectivity issue in my layout hierarchy. For demonstration I've recreated the problem of my layout in a few pictures. The problem is with the connectivity of PIN's. If I have 2 cells, each with a pin and I connect them together using intersecting metal, no connection is...

Part and Inventory Search

Back
Top