Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi everyone,
In the FIFO of IP core, I see that the read clock and write clock of asynchronous FIFO should be free-running to ensure it work correctly.
In my project, I used the Aurora Protocol 2 lanes with (lane 1: X0Y3_GTP0 and lane 2: X0Y4_GTP1) with GT REFCLK is 60 MHz.
In the...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.