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Re:Synthesis Help
@ Engineer_Bob
iam writing code..
and i am using xilinx ise 8.1i demo version ....
and thats the reason i had a doubt....
i thought i would get some expert advice...
before investing on any tool...thats it
Added after 20 minutes:
From
MentorGraphics.com we have...
Dear Experts ,
Iam into a designing of core IP and sucessfully completed it using verilog
and functional verification is done using Modelsim se 6.0.
My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version and the gatecount was something around...
Dear Experts ,
Iam into a designing of core IP and sucessfully completed it using verilog
and functional verification is done using Modelsim se 6.0.
My IP core has 5 main modules of which I synthesized 1 module using xilinx ISE 8.1i demo version
and the gatecount was something around 122k
Now...
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