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Hi All,
what constraint to be used in Spyglass DFT to make LATCH as transparent during capture mode.
I tried adding test_mode signal to enable pin of latch. this is giving Scan_07 errors.
Thanks,
Amar.
Hi All,
i have port ex "bus [10:0]"
i need to generate a VCD dump like
"$var wire 48 #/ _bus [10:0] $end"
but the tool(incisiv 14.1) is generating like
"$var wire 10 #/ _bus [10] $end"
"$var wire 9 $/ _bus [9] $end"
"$var wire 8 %/ _bus [8] $end"
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